1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device capable of electrically performing read and write operations and method for reading an information from the non-volatile semiconductor memory device.
2. Description of the Related Art
In recent years, techniques related to an electrically erasable non-volatile memory have been rapidly developed, and its variety of applications have been found. A E.sup.2 PROM which is a typical example of a non-volatile memory is capable of electrically erasing data and has a high read speed. In the E.sup.2 PROM, however, a write speed is low, and write/erase cycles are limited.
For this reason, a ferroelectric memory has been recently developed. The ferroelectric memory comprises a plurality of memory cells each having a capacitor using a ferroelectric material as a dielectric. Directions of remanent polarization of the ferroelectric material correspond to data of "0" and "1", and the data is stored in each memory cell. When data is written in the ferroelectric memory, a voltage which is much higher than a coercive electric field is applied to a ferroelectric capacitor of each memory cell in a direction corresponding to desired data. The PG,3 ferroelectric material is polarized in a direction of the applied voltage, and a part of the polarization remains as remanent polarization after removing the voltage. In addition, when data are read out from the memory cell, a voltage which is much higher than that the coercive electric field is applied to the ferroelectric capacitor of the memory cell in a predetermined direction. When the applied voltage has the same direction as that during write access, polarization is slightly changed, thereby supplying a slight charge current to the ferroelectric capacitor. In contrast to this, when the applied voltage has an opposite direction to the voltage during write access, since remanent polarization is reversed, polarization is largely changed, thereby supplying a large charge current. Therefore, by reading a current amount, data written in each cell is determined to be data of "0" or "1". It is reported that read/write speeds of a ferroelectric memory are several tens nsec. Therefore, the ferroelectric memory can respond at a high speed. The above ferroelectric memory is disclosed in, e.g., U.S. Pat. No. 3,939,292.
However, the above conventional ferroelectric memory has the following problems.
(1) As described above, in the ferroelectric memory, once a read operation is performed, remanent polarization formed in a ferroelectric capacitor has the same direction as a voltage applied for read access independently of a direction of a voltage applied for write access. By this remanent polarization, written data is determined. However, stored data is lost according to this read operation. This read access method is called destructive read access. In order to retain data in the memory cell after its destructive read access, the same data is written in the ferroelectric capacitor of the memory cell again after determining the readout data. In contrast to this, the above E.sup.2 PROM employs nondestructive read access in which data is not lost upon read access. When the destructive read access method is performed in a conventional ferroelectric memory, the circuit is complicated compared with the nondestructive read access since a rewrite operation is required. PA1 (2) As described in the above problem (1), since the rewrite operation must be performed in the ferroelectric memory after read access, the direction of polarization of a ferroelectric capacitor is frequently and repeatedly reversed. When reversing of polarization is frequently repeated, ferroelectricity of the ferroelectric material is gradually degraded, thereby decreasing remanent polarization. This phenomenon is called "wear out". It can be understood that this wear out of the ferroelectric material appears by repeatedly reversing spontaneous polarization 10.sup.12 times. When the wear out which decreases the remanent polarization appears, a charge current difference between data of "0" and "1" is decreased during read access. Therefore, the data can hardly be determined. In the ferroelectric memory, its service life is defined by the wear out. Thus, a conventional ferroelectric memory in which polarization is repeatedly reversed to rewrite data after read access has a short service life. PA1 a memory cell having a semiconductor-ferroelectric junction capacitor formed by stacking a semiconductor layer and a ferroelectric layer between a pair of electrodes, the semiconductor layer and the ferroelectric layer forming a semiconductor-ferroelectric junction; PA1 a writing means, in response to a voltage which is higher than a coercive electric field of the ferroelectric layer and is applied to the capacitor of the memory cell, for aligning a polarization direction of the ferroelectric layer in a predetermined direction to set a capacitance of the capacitor at a predetermined value, and for writing data corresponding to the predetermined value of the capacitance; and PA1 a reading means, in response to a voltage which is less than the coercive electric field of the ferroelectric layer and is applied to the capacitor of the memory cell in which the data is written, for reading the data. PA1 (a) The capacitor includes: PA1 (b) The capacitor includes: PA1 (c) The capacitor includes: PA1 (d) A capacitor includes a so-called stacked structure formed by stacking at least one capacitor having the structure (a) or (b) on a semiconductor substrate having a capacitor of the structure (c) through an insulating layer. PA1 a memory cell having a capacitor formed by stacking a semiconductor layer and a ferroelectric layer between first and second electrodes to form a semiconductor-ferroelectric junction by said semiconductor layer and said ferroelectric layer; PA1 a plate line, connected to said first electrode, for applying a first voltage to said first electrode; PA1 a bit line for applying a second voltage to said second electrode, data stored in said memory being read out into said bit line during read access; PA1 first switching means connected between said second electrode; PA1 a word line for supplying a first switching signal to said first switching means; PA1 supply means for supplying a voltage lower than a coercive electric field of said ferroelectric layer to said second electrode during read access; PA1 second switching means connected between said second electrode and said supply means; and PA1 a selection line for supplying a second switching signal to said second switching means, PA1 said method comprises the steps of: PA1 setting a voltage of said bit line at a reference voltage; PA1 turning said second switching means on to apply a voltage lower than said coercive electric field of said ferroelectric layer to said second electrode; and PA1 turning said first switching means on to read out said data stored in said memory into said bit line. PA1 a plurality of memory cells each having a capacitor formed by stacking a semiconductor layer and a ferroelectric layer between first and second electrodes, said semiconductor layer and said ferroelectric layer forming a semiconductor-ferroelectric junction; PA1 first selection means for selecting a predetermined memory cell from said plurality of memory cells; PA1 a plurality of reference memory cells, having third and fourth electrodes, for storing reference data to be compared with storage data in said plurality of memory cells; PA1 second selection means for selecting a predetermined reference memory cell from said plurality of reference memory cells; PA1 first voltage applying means for applying a first voltage to said first electrode of the selected memory cell; PA1 reference voltage applying means for applying a reference voltage to said third electrode of the selected reference memory cell; PA1 second voltage applying means for applying a second voltage lower than a coercive electric field of said ferroelectric layer to said second electrode during read access; and PA1 write/read means for writing data in said selected memory cell during write access and reading said data from said selected memory cell and said reference data from said selected reference memory cell during read access, PA1 said method comprises the steps of: PA1 setting a voltage across said first and second electrodes of said selected memory cell at 0 V; PA1 setting a voltage of said write/read means with respect to said second electrode at a value lower than said coercive electric field of said ferroelectric layer; and PA1 reading out said data and reference data into said write/read means.